The Z80 family of integrated circuits manufactured by Zilog, Inc. includes not only the Z80 microprocessor (which designation is used herein to denote the original Z80 microprocessor and, except where the context might otherwise require, subsequent versions such as the Z80A and Z80H) but also peripheral devices such as the Z80 SIO (serial input/output), the Z80 PIO (parallel input/output) and the Z80 CTC (counter-timer). The different peripheral devices are specifically designed to function with the Z80 microprocessor and to be connected to the data bus of the Z80.
It is well understood that a microprocessor operates by executing a sequence of instructions. From time to time, it may be desirable to interrupt a particular operation to perform an interrupt routine, and upon completion of the interrupt routine the microprocessor resumes the interrupted operation. The Z80 executes each instruction cycle in one or more machine cycles. Each instruction cycle includes at least one op code fetch cycle (M1). During the last machine cycle of each instruction, the microprocessor samples its /INT pin, and if the /INT pin is low the microprocessor completes its current instruction cycle and then enters a special M1 state, in which its /M1 pin goes low. While the /M1 pin remains low, the /IORQ pin also goes low, and the coincidence of /M1 and IORQ both being low constitutes an interrupt acknowledge cycle. The interrupt acknowledge cycle indicates that the Z80 is ready to service an interrupt. The Z80 has three possible interrupt modes, the most flexible of which is known as the mode 2 interrupt. In the mode 2 interrupt, the peripheral places an address vector on the data bus, and the CPU addresses the memory location defined by the address vector and executes the interrupt routine stored at that location.
If there is more than one peripheral connected to the Z80 data bus, the several peripherals may be connected in a so-called daisy chain. Each of the Z80 peripherals has an interrupt enable in (IEI) pin and an interrupt enable out (IEO) pin, and the peripheral devices are arranged hierarchically with the IEO pin of the device that is higher in the hierarchy connected to the IEI pin of the next lower device. In a conventional daisy chain, the IEI pin of the highest order device is tied to logical 1. When a peripheral device receives logical 1 at its IEI pin and does not itself wish to make an interrupt, it provides logical 1 at its IEO pin, thus applying logical 1 to the IEI pin of the next lower device in the daisy chain. In order to perform an interrupt, a peripheral device must receive logical 1 at its IEI pin and must detect an interrupt acknowledge cycle from the Z80. During the interrupt acknowledge cycle, the peripheral removes the logical 0 from its /INT pin, letting that pin go high, and places a vector on the data bus.
Hitherto, it has not been possible for devices other than peripheral devices in the Z80 family to interact with a Z80 microprocessor through its interrupt capability. This implies that if it is desired that a non-Z80 peripheral device should interact with a Z80 microprocessor, it must do so through a Z80 peripheral device, and therefore the output of the non-Z80 peripheral device must conform to the input requirements of the Z80 peripheral device. Moreover, use of an additional peripheral device may cause delay in executing the interrupt routine.